1. Field of the Invention
The embodiments of the invention generally relate to a stress memorization method for field effect transistors and, more particularly, to a stress memorization method for fin-type or trigate field effect transistors.
2. Description of the Related Art
The mobility of the charge carriers through the channel region of a metal oxide semiconductor field effect transistor (MOSFET) directly affects performance. Specifically, carrier mobility affects the amount of current or charge which flows, e.g., as electrons or holes, in the channel region. Reduced carrier mobility can reduce the switching speed of a given transistor. Reduced carrier mobility can also reduce the differences between the on and off states and can, therefore, increase susceptibility to noise. Various techniques have been used to improve the charge carrier mobility in such devices.
For example, planar complementary metal oxide semiconductor (CMOS) devices have been able to benefit from increased mobility with a technique known as Stress Memorization Technology. This technology uses mechanical stress control of the channel regions to enhance hole mobility in p-type FETs (p-FETs) and electron mobility in n-type FETs (n-FETs). Uni-axial tensile strain (parallel to the direction of the current) in the channel region increases electron mobility and decreases hole mobility, while uni-axial compressive strain (parallel to the direction of the current) in the channel region increases hole mobility and decreases electron mobility.
Specifically, referring to FIG. 1, the technique begins with a planar FET structure 200. The FET 200 comprises a channel region 230 disposed between source/drain regions 220 in a silicon layer of a wafer and also comprises a polysilicon gate 210 above the channel region 230 (102, see FIG. 2a). After the gate 210 and source/drain regions 220 of the FET 200 are formed, an appropriately selected straining layer 250 is deposited over the FET structure (106, see FIG. 2c). For example, a compressive straining layer can be deposited over a p-FET to and a tensile straining layer can be deposited over an n-FET.
Either before or after the straining layer 250 is formed, an amorphization implant process is performed in order to amorphize both the silicon of the source/drain regions 220 and the gate polysilicon 210 (104, see FIG. 2b). A rapid thermal anneal process is used to re-crystallize the silicon source/drain regions 220 and the polysilicon gate 210 such that the strain of the straining layer 250 is ‘memorized’ in the silicon and polysilicon of the source/drain regions 220 and gate 210, respectively. By inducing either a tensile or compressive strain into the source/drain regions and into the gate, a similar strain is imparted on the channel region 230 (108). Additionally, the straining layer 250 can be removed (110) and a second straining layer can be deposited on the over the wafer surface with a net benefit above that attainable with just a simple deposited straining film (112).
Unfortunately, this stress memorization technique does not transfer over to non-planar FETs (e.g., dual gate FETs, such as fin-type FETs, or trigate FETs) in a straightforward fashion. Therefore, there is a need in the art for a stress memorization technique suitable for use with non-planar FETs.